A disciplined oscillator system having a standard oscillator which is automatically corrected for both frequency errors and time error accumulation to a constant frequency signal which is derived from the WWVB carrier frequency and the WWVB TIME CODE to maintain overall frequency accuracy within one part in 109 notwithstanding oscillator aging and in spite of jitter and distortion due to propagation delays and noise which may cause loss of, or time jitter in, the WWVB signals.
Frequency errors are detected through the use of a counter (24) having a measurement accuracy greater than one part in 1010. An error detector (26) derives correction signals by averaging a plurality of frequency variances obtained in successive measurement cycles. Timing errors are corrected by dividers (34, 40) controlled by a timing discriminator (36) which responds to timing variance between signals from the standard oscillator and from the WWVB reference which are phase locked to those TIME CODE signals which are substantially free of noise and jitter.
The timing correction is inhibited after the standard oscillator is corrected. Frequency correction is applied continuously.
The present design relates to systems for providing signals with highly stable constant frequency, sometimes called frequency standards, and particularly to systems where high stable signals are obtained from an oscillator, the stability in frequency and/or time is controlled by a reference signal having known precision, which oscillator may be called a disciplined oscillator.
The design is especially suitable for use in providing frequency standard or precision time-base standard signals having their stability traceable to a reference frequency obtained from a broadcast transmission, particularly the transmissions of the National Bureau of Standards (NBS) reference frequencies and TIME CODE signals which are transmitted by radio station WWVB.
The design is also applicable for use with reference frequencies obtained from other sources, such as via satellite transmissions and from master reference sources which may be cesium or other atomic standards. When NBS and WWVB are mentioned, such mention should be taken to mean equivalent transmissions, such as from radio station MSF in England, which is operated by the British Government.
Standard frequency sources have been provided with local, highly stable oscillators. The outputs of these oscillators may be compared with signals phase locked to signals received from WWVB and deviations recorded so as to make errors visible and correctable by manual control from time to time.
The NBS frequency standard receiver model 8161 available from Spectracom Corporation, Rochester, N.Y. provides such a standard frequency source with precision traceable to NBS. Disciplined oscillator systems have also been available which are phase locked to external reference signals such as derived from atomic standards (usually cesium).
The standard oscillators which are disciplined are themselves highly stable. The frequency errors with respect to the reference frequency are due principally to long term phenomena, such as aging of components in the oscillator. Deriving corrections of frequency and timing in the long term, over long periods of time, so as to maintain stability to extremely high resolutions, for example one part in 109 or better, is extremely difficult, particularly when the components used may result in long term errors of similar magnitude.
The problem is exacerbated when the reference signals come from broadcast transmissions, such as the NBS WWVB transmission. Propagation delays and noise perturb these transmissions making it difficult to obtain reliable reference signals.
Accordingly it is a principal object of the present design to provide an improved disciplined oscillator system wherein a standard oscillator is automatically and continuously adjusted to maintain a standard frequency output in accordance with a reference signal.
It is another object of the present design to provide an improved disciplined oscillator system, the output signal of which is maintained highly stable in frequency and timing with respect to a broadcast reference signal, such as the NBS WWVB transmission.
It is a still further object of the present design to provide an improved disciplined oscillator system which automatically compensates a standard oscillator, which is itself highly stable, in frequency to the precision of a reference signal on a long term basis.
It is a still further object of the present design to provide an improved disciplined oscillator system which makes use of a microprocessor in deriving frequency and/or timing error signals for controlling the oscillator to maintain it stable in frequency with respect to a reference signal automatically and continuously over long periods of time.
It is a still further object of the present design to provide an improved disciplined oscillator system having a standard oscillator which is automatically adjusted in accordance with received broadcast reference signals, such as signals broadcast by the NBS WWVB station, which maintains its frequency accuracy in spite of the absence of reliable transmissions of the reference signal from time to time.
Briefly described, a disciplined oscillator system embodying the design includes a standard frequency oscillator for providing a standard frequency output and having an input for controlling the frequency thereof. Frequency controller means are responsive to constant frequency signals, which may include pulses which are repetitive at fixed intervals of time.
These signals may be derived from a receiver which is phase locked to broadcast reference frequency signals which may include pulses, such as represent time codes, which are repetitive at fixed intervals of time (e.g., each second). The frequency controller may include a counter having capacity to count a number greater than the resolution in frequency to which the standard frequency output is to be controlled.
Means responsive to the constant frequency signals, repetitively enable the counter to count the standard frequency output during successive intervals, each of length sufficient to count a number of cycles of the standard frequency output at least equal to the desired frequency resolution.
Means responsive to the counts stored in the counter, for example a microprocessor, processes the counts to provide the frequency control signal which is applied to frequency control input of the oscillator. The system may include time controller means which are responsive to the fixed interval (time code) pulses for detecting time displacements of the standard frequency output with respect to these pulses for providing a timing control signal.
The timing controller means makes use of means responsive to the constant frequency signals and the pulses for providing a train of reference pulses, phase locked to the fixed interval pulses. The timing control signals are obtained by means responsive to the phase difference between the fixed interval pulses and the reference pulses.
Only fixed interval (TIME CODE) pulses which are substantially free from jitter and noise perturbations are utilized to develop the timing control signals. These signals are applied to the frequency control input of the standard oscillator until the removal of timing errors from the standard frequency output is detected in response to the phase difference between the fixed interval pulses and the reference pulses.
Then, the frequency control means continues to provide long term stability in the standard frequency output. The disciplined oscillator is thereby provided with a stability of one part in 109 on a long term basis.
Referring first to FIG. 1, there is shown a WWVB receiver 10 connected to an antenna 12 which receives the 60 KHz WWVB transmission. The receiver provides a reference output, which is phase locked to the NBS transmission, in the form of a 10 MHz signal called NBS 10 MHz. The receiver also demodulates the TIME CODE signals which are transmitted by a reduction in the 60 KHz carrier level each second.
These TIME CODE signals are pulses either 200, 500 or 800 milliseconds in duration (wide). The 200 millisecond pulse represents a logical zero bit. The 500 millisecond pulse represents a logical one bit and the 800 millisecond pulse represents a position identifier. The TIME CODE signals may be used to derive the time of day and day of the year.
They are used in accordance with this design for time error control purposes. The design of the receiver 10 may be similar to the Spectracom 8161 frequency standard receiver.
The system also uses a standard oscillator 14 which is frequency disciplined. This oscillator provides a standard 10 MHz output frequency which is maintained accurate to a high degree of precision at least one part in 109. The oscillator 14 is disciplined or adjusted with control signals derived with respect to the NBS reference transmitted by WWBB.
This reference is accurate to within one part in 1011. Day to date deviations in frequency are nominally less than one part in 1012. However, changes in the propagation medium, for example, with atmospheric and stellar conditions, result in fluctuations in the WWVB carrier which are received by the receiver 10 that may be much greater than the inherent accuracy of the NBS reference.
The disciplined oscillator system accommodates for such uncertainty in the standard in large measure. The oscillator 14 is a quartz crystal oscillator which may be contained in a temperature controlled oven. Its circuit includes a variable reactance element (e.g. a varactor diode) which enables the frequency to be varied over a range sufficient to overcome the long term instability of the oscillator.
The oscillator has good short term stability, but may vary in frequency over the long term (a day or more). The frequency may be adjusted over a ten Hz range for example by the control signal, which is inputted to the oscillator 14. The oscillator may be of a design used in the Spectracom 8161 standard frequency source.
The control signals for disciplining the oscillator 14 are obtained from a frequency controller 16 and also from a time controller 18. While the system preferably includes both the frequency controller 16 and the time controller 18, the standard oscillator 14 may obtain its control signals either from the frequency controller 16 or the time error controller 18 alone.
When the system is provided without the time error controller 18, frequency controller will continue to be provided, but without correction for variances of the standard 10 MHz output from the oscillator 14 with respect to the TIME CODE signals.
In the frequency controller 16, the NBS 10 MHz signal is used to operate a gate generator 20 which generates a gate signal of 1000 seconds in duration. This gate signal is synchronous with a timing signal derived from the NBS 10 MHz signal by a timer 22. This timing signal is suitably a pulse which is repetitive at 5 millisecond intervals.
The gate signal from the generator 20 is synchronous with these timing pulses. Each gate is separated from its succeeding gate by the portion of 5 milliseconds between the end of the preceding 1000 second gate and the beginning of the succeeding 1000 second gate. Thus, the gate has a relatively long duty cycle.
A counter 24 is enabled by the 1000 second gate and is clocked by the STD 10 MHz signal from the standard oscillator 14. The counter 24 has a count capacity at least equal to the resolution to which the frequency is to be controlled in order to provide a resolution of one part in 1010, a 48 bit binary counter, which is capable of counting more than 10 billion cycles of the STD 10 MHz signal, is used.
The counter 24 thus provides a resolution exceeding one part in 1011. The lower order (least significant) bit of the counts stored in the counter after each 1000 second gate, thus represent variances in the frequencies of the STD 10 MHz signal.
An error detector 26, the operation of which is timed by the timer signals interrogates the counter for variances exceeding one part in 109 in a plurality, suitably four, consecutive 1000 second gates. If the variance is one part in 109 or less, the three variances are averaged and the output is applied to a correction level generator 28.
It will be apppeciated that 10 million cycles of the STD 10 MHz signal are presented for counting in the counter 24 during each 1000 second gate. The variance is represented by the difference in the count from exactly 10 million. Only if variances on consecutive gates are one part in 109 or less is the error used to obtain a frequency correction signal in the correction level generator 28.
For larger corrections, which exceed one part in 108, a fault detector 30 is actuated which operates an alarm 32 to indicate that the frequency of the STD 10 MHz signal is in error by more than one part in 108. The operator may then attempt to control the frequency of the standard oscillator 14 manually.
Alternatively, the fault detector may operate a switch (not shown) to switch over the output of the system to a standby or auxilliary disciplined system. Two disciplined oscillator systems may be used, one backing up the other, in the interest of enhancing reliability.
The correction level generator 28 suitably includes a digital to analog (D/A) converter which translates the digital error signal from the counter 24 into the frequency control signal. In the case of the illustrated system, where the standard oscillator 14 has a 10 Hz tuning range subject to correction by signals derived during the 1000 second gate, the resolution of the correction is 10,000 parts.
The D/A converter in the generator 28 may suitably be a 12 bit multiplying digital to analog converter. The error signal may be processed so that each of the 4,096 or 212 possible increments in the analog output are related to the 10,000 possible parts by multiplying the measured error by 4096 and dividing their product by 10,000.
This processing may be carried out by discrete logic elements or in a microprocessor. The frequency correction signal may vary incrementally to a small extent, since it is indicated by the counts stored in the counter 24 during consecutive 1000 second intervals. The adjustment in the frequency of the standard oscillator 14, therefore, occurs slowly and in a manner to make up for the long term frequency variations in its STD 10 MHz output.
By utilizing readings (stored counts) from the counter 24 only when three out of four cqnsecutive readings (over a interval exceeding 4000 seconds) which have variances of one part in 109 or less and then only the average of such readings, the average error in the STD 10 MHz signal is obtained fully to a resolution of one part in 1010, which is the full resolution capacity of the frequency controller 16 obtainable by counting a 10 MHz signal during a 1000 second gate.
The time error controller 18 uses a first chain of dividers 34 which divides the NBS 10 MHz signal down to a 1 Hz signal called NBS 1 Hz. The TIME CODE signals are processed in a noise and jitter discriminator 34 so as to obtain pulses each second which are substantially free from noise and jitter due to propagation delays, interference and inter-symbol distortion.
The TIME CODE signals repeat at fixed intervals of one second and may be referred as fixed interval signals. NBS 1 Hz is derived from the NBS WWVB transmissions and may be referred to as reference pulses. The TIME CODE, fixed interval pulses which are reliable indications of the one second timing, which is accurate to the NBS transmission, are selected by the discriminator 35.
Pulses which jitter due to inter-symbol distortion are eliminated by selecting only the TIME CODE pulses which follow a logical zero (the fixed interval of one second when a 200 millisecond pulse is transmitted). When a preceding TIME CODE pulse is a logical one (500 milliseconds), or a PID (800 milliseconds), it is not used and the operation of the time error controller is not dependent thereon.
The leading edge of the TIME CODE pulse is exactly at the one second intervals. The only pulses having precisely defined edges are used to discriminate against noise and jitter. In the discriminator 35 the TIME CODE pulses may be sampled every 5 milliseconds with timing pulses from the timer 22.
Only if there are a given number, say 16, samples of one polarity followed by 16 samples of the opposite polarity (16 low samples followed by 16 high samples), is a TIME CODE pulse selected. The discriminator 35 may also count the number of good pulses for use in operation of the controller 18.
A timing discriminator 36 detects the relative time displacement between the fixed interval TIME CODE pulses and the NBS 1 Hz pulses. The dividing ratio in the dividers 34 is changed in accordance with the time relationship between the NBS 1 Hz and the fixed interval TIME CODE pulses so as to phase lock the NBS 1 Hz to the fixed interval TIME CODE pulses.
A number of outputs from the timing discriminator 36 are counted in a counter 38. The counter may be an up down counter. If after this number of counts, corresponding to several repetitions of the 1 Hz signals, the number of outputs from the discriminator 36 indicates a leading or early relationship of NBS 1 Hz to the fixed interval TIME CODE pulses, the dividing ratio is increased so as to make the NBS 1 Hz pulses arrive later in time.
Conversely, if the count in the counter represents a lagging relationship the dividing ratio is decreased so as to make the NBS 1 Hz pulses arrive earlier. In the interest of rapidly bringing the NBS 1 Hz into phase lock with the fixed interval TIME CODE signals, the number of 1 Hz repetitions (the number of seconds) when the counter 38 counts the outputs of the timing discriminator 36 may be varied.
A good pulse counter in the discriminator 35 may set the number, initially for a low number of good pulses, after which time the dividing ratio may be changed maximally to delay or advance the NBS 1 Hz pulses by a maximum period of time. Then, as the delay or advance of the NBS 1 Hz exceeds that which is required to bring about phase lock with the TIME CODE fixed interval signals, the sense of the output of the timing discriminator 36 will change, for example from a lagging condition to a leading condition.
This change or cross-over is utilized to increase the number of good pulses which must be counted in the counter 38 before the dividing ratio in the divider 34 is altered. The dividing ratio is then changed by a smaller amount. The process continues with each cross-over until a very large number of 1 Hz pulses, for example over 1000, is counted in the counter 38 until a change of the dividing ratio in the dividers 34 is effected.
Ultimately, the change in dividing ratio must be in its lowest order digit corresponding to a very small advance or delay (20 microseconds as will be apparent hereinafter from FIG. 2) as phase lock is reached the dividing ratio may change by one increment in the lowest order digit each time the very large number of good time code pulses is counted.
Upon phase lock, the dividing ratio of the dividers 34 is transferred to another divider chain 40 which divides the STD 10 MHz signals from the standard oscillator 14 down to 1 Hz signals, called STD 1 Hz. Preferably the dividing ratio of the dividers 40 is set by means of an accumulating phase detector 42 which accumulates timing pulses obtained from the dividers 34 which may be repetitive at 20 microsecond intervals.
The dividing ratio is changed opposite senses depending upon whether the NBS 1 Hz signal is leading or lagging the STD 1 Hz signal. The accumulated phase error is transferred to the dividers 40 at the time of a cross-over from a leading to lagging condition of the NBS 1 Hz and STD 1 Hz signals derived by another timing discriminator 44 and a cross-over detector 46 which responds to the sense of the output of the timing discriminator 44.
It is preferable to use the accumulating phase detector 42 to set the dividers 40 which produce the STD 1 Hz instead of transferring the dividing ratio which is set into the dividers 34 which produce the NBS 1 Hz, since the latter dividing ratio changes from time to time. The output of the accumulating phase detector may also be used to detect if there has been a gain or loss of more than plus or minus 2 milliseconds in the timing of the NBS 1 Hz with respect to the STD 1 Hz.
Then the alarm 32 is activated. The alarm 32 is inhibited until the dividing ratio is set into the STD 1 Hz dividers 40.
A time correction offset generator provides an incremental time correction corresponding either to plus or minus one part in 109 of the frequency of the standard oscillator 14 depending upon whether the timing discriminator 44 indicates that the NBS 1 Hz is lagging or leading the STD 1 Hz.
This incremental timing correction is applied to the correction level generator 28 after the error detector 26 inputs a frequency error correction output to the correction level generator 28. Then the time correction offset generator 48 is enabled. The frequency of the standard oscillator 14 is controlled by the time correction signal generated in the correction level generator 28.
Eventually the cross-over detector 46 will detect a cross-over when the time relationship between the STD 1 Hz and NBS 1 Hz changes. The time correction offset generator is then inhibited since the time errors have been substantially removed from the standard oscillator and it is time coherent with the TIME CODE signals and to the accuracy of the NBS transmission.
The disciplined oscillator system is preferably microprocessor based, utilizing a microprocessor 50 to implement or control the components of the disciplined oscillator system. The microprocessor based disciplined oscillator system is illustrated in FIG. 2.
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